1. Field of the Invention
The invention relates generally to the field of integrated circuit (IC) device packaging technology, and more particularly to the cooling of hotspots on IC semiconductor die, heat spreading for IC packages, and thermal interconnection technology in IC packaging.
2. Background Art
Electronic signals are carried by electrical current through conductors and transistors in a large scale integrated circuit (IC) fabricated on semiconductor substrate. The energy carried by the electrical current is partially dissipated along the paths of current flow through the IC in the form of heat. Heat generation in electronic semiconductor ICs is also known as power consumption, power dissipation, or heat dissipation. The heat generated, P, in an IC is the sum of dynamic power, PD, and static power, PS:P=PD+PS=ACV2f+VIleak where A is the gate activity factor, C is the total capacitance load of all gates, V is the peak-to-peak supply voltage swing, f is the frequency, and Ileak is the leakage current. The static power term, PS=VIleak, is the static power dissipated due to leakage current, Ileak. A further description regarding static power is provided in Kim et al, Leakage Current: Moore's Law Meets Static Power, IEEE Computer, 36(12): 68-75, December 2003, which is incorporated by reference herein in its entirety.
The dynamic power term, PD=ACV2f, is the dynamic power dissipated from charging and discharging the IC device capacitive loads. Dynamic power consumption is thus proportional to the operating frequency and the square of operating voltage. Static power consumption is proportional to the operating voltage. Advances in transistor gate size reduction in semiconductor IC technology have reduced the operating voltage and power dissipation for single transistors. However, on-chip power densities are expected continue to rise in future technologies as the industry continues to follow the trend set forth by Moore's Law. In 1965, Intel co-founder Gordon Moore predicted that the number of transistors on a chip doubles about every two years. In addition to the increased number of transistors on a chip, the operating frequencies also double about every two years according to the 2004 International Technology Roadmap for Semiconductors (ITRS Roadmap) (http://www.itrs.net/Common/2004Update/2004—00_Overview.pdf). Because of the increased difficulties in controlling noise margins as voltage decreases, operating voltages can no longer be reduced as quickly as in the past for 130 nm gate lengths and smaller. Consequently, on-chip power dissipation will continue to rise. See Table 6 of the ITRS Roadmap. With the increased use of 65 nm technology in foundry processes and the commercialization of 45 nm technology, power consumption is now a major technical problem facing the semiconductor industry.
Another characteristic of IC chips is the uneven distribution of temperature on a semiconductor die. More and more functional blocks are integrated in a single chip in system-on-chip (SOC) designs. Higher power density blocks create an uneven temperature distribution and lead to “hotspots,” also known as “hot blocks,” on the chip. Hotspots can lead to a temperature difference of about 5° C. to roughly 30° C. across a chip. Further description of hotspots is provided in Shakouri and Zhang, “On-Chip Solid-State Cooling For Integrated Circuits Using Thin-Film Microrefrigerators,” IEEE Transactions on Components and Packaging Technologies, Vol. 28, No. 1, March, 2005, pp. 65-69, which is incorporated by reference herein in its entirety.
Since carrier mobility is inversely proportional to temperature, the clock speed typically must be designed for the hottest spot on the chip. Consequently, thermal design is driven by the temperature of these on-chip hotspots. Also, if uniform carrier mobility is not achieved across the IC die due to on-chip temperature variations across the die, this may result in variations in signal speed and in complicating circuit timing control.
Heat spreaders, including drop-in heat spreaders, heat sinks, and heat pipes have been used in the past to enhance thermal performances of IC packages. Further descriptions of example heat spreaders are provided in U.S. Pat. No. 6,552,428, entitled “Semiconductor Package Having An Exposed Heat Spreader”, issued Apr. 22, 2003, which is incorporated by reference herein in its entirety. Further descriptions of example heat pipes are provided in Zhao and Avedisian, “Enhancing Forced Air Convection Heat Transfer From An Array Of Parallel Plate Fins Using A Heat Pipe, Int. J. Heat Mass Transfer, Vol. 40, No. 13, pp. 3135-3147 (1997).
For example, FIG. 1A shows a die up plastic ball grid array (PBGA) package 100 integrated with a drop-in heat spreader 104. In package 100, IC die 102 is attached to a substrate 110 by die attach material 106 and is interconnected with wirebond 114. Package 100 can be connected to a printed wire board (PWB) (not shown) by solder balls 108. A drop-in heat spreader 104 is mounted to substrate 110, and conducts heat away from die 102. Mold compound 112 encapsulates package 100, including die 102, wirebond 114, all or part of drop-in heat spreader 104, and all or part of the upper surface of substrate 110. Drop-in heat spreader 104 is commonly made of copper or other material that is thermally more conductive than mold compound 112. Thermal conductivity values are around 390 W/m*° C. for copper and 0.8 W/m*° C. for mold compound materials, respectively.
Thermal enhancement methods, such as shown in FIG. 1A, rely on heat removal from the entire chip or from the entire package. They maintain semiconductor temperature below the limit of operation threshold by cooling the entire chip indiscriminately. These methods are often ineffective and inadequate to reduce the temperature of the hotspots relative to the rest of the chip, such that operation of the chip is still limited by the hotspots.
For example, FIG. 1B shows a perspective view of a silicon die 102, and in particular shows the temperature distribution on silicon die 102 in a PBGA with no external heat sink. The temperature difference across the die 102 is 13.5° C. FIG. 1C shows die 102 of FIG. 1B, illustrating the effect of adding a drop in heat spreader and a heat sink to the package of die 102. The temperature difference remains 13.0° C. with a large size (45 mm×45 mm×25 mm) external aluminum pin-fin heat sink attached on top of the exposed drop-in heat spreader. Both the drop-in heat spreader and the external heat sink are ineffective to reduce the on-chip temperature differences caused by the hot spots.
Active on-chip cooling methods that use electrical energy to remove heat from the IC chip are known in the art. For example, some have suggested pumping liquid coolant through micro-channels engraved in silicon to circulate on the semiconductor die and carry away waste heat. A further description regarding liquid cooling is provided in Bush, “Fluid Cooling Plugs Direct onto CMOS,” Electronic News, Jul. 20, 2005, http://www.reed-electronics.com/electronicnews/article/CA626959?nid=2019 &rid=550846255), which is incorporated by reference herein in its entirety. See also Singer, “Chip Heat Removal with Microfluidic Backside Cooling,” Electronic News, Jul. 20, 2005, which is incorporated by reference herein in its entirety.
Other active cooling methods have been developed in an attempt to provide active on-chip cooling using a thin-film thermoelectric cooler (TEC). A further description regarding on-chip cooling with TECs is provided in Snyder et al, “Hot Spot Cooling using Embedded Thermoelectric Coolers,” 22nd IEEE SEMI-THERM, Symposium, pp. 135-143 (2006), which is incorporated by reference herein in its entirety.
These active cooling methods require exotic and expensive fluid circulation or micro-refrigeration systems and add to the total power consumption of the package that must be removed. A separate power supply must also be integrated into the IC package to drive the fluid pumping or the TEC systems. These can be costly and can decrease component reliability. Because these solutions are typically expensive, their use is limited in cost sensitive applications such as consumer electronic devices.
These cooling methods as discussed above are inadequate and/or difficult and expensive to implement for commercial applications. What is needed is an inexpensive and reliable system and method of selective heat removal from hot blocks or hotspots on semiconductor dice.